Field of the Invention
The invention relates to a memory circuit, in particular a pseudostatic memory circuit. The invention furthermore relates to a method for operating a memory circuit.
Pseudostatic memory circuits are utilized for example in low power applications for future mobile telephones. A large number of functionalities having a high memory requirement are realized in these mobile telephones. The high memory requirement arises for example as a result of video or image representation and also as a result of Internet capability.
Static random access memories (SRAMs) have hitherto been used in these devices in order to cover the memory requirement.
SRAMs have a comparatively high current consumption and will be replaced in the future by so-called pseudostatic memories (PSRAMs). A PSRAM is a DRAM memory that is operated like a static memory. For the same memory density, PSRAMs have a much smaller chip area and, moreover, require less electrical energy for storing data.
Therefore, one goal has been to develop PSRAMs such that they can replace the SRAMs that are used in present-day systems. In this case, the system environment (interfaces, signal configurations) shall preferably remain unchanged so that complex adaptations can be avoided.
Since pseudostatic memories are based on DRAM architectures, i.e. they have dynamic memory cells, the memory cells have to be refreshed in order to retain the memory information as in a normal DRAM memory. In conventional DRAM memories, the refresh operation is controlled by the system environment and not by the DRAM memory. This is not the case with conventional SRAMs. For this reason, PSRAMs must have a dedicated refresh unit by which the memory cells of the PSRAM can be refreshed independently in order to retain the memory information.
Furthermore, it is necessary to provide a refresh controller that ensures that no collision occurs between an internally generated refresh access and an external read/write access. The refresh controller additionally has to ensure that an internal refresh operation does not restrict the functionality. The refresh should be invisible to the user or to the system environment, i.e. not be brought about by a restriction of the functionality.
Such a refresh controller is possible only with restrictions, however, because usually specific SRAM accesses are possible which inevitably entail a violation of the refresh period. The refresh period is determined from the number of cells and the architecture of the memory and determines the time in which a memory cell must be refreshed again in order that the information stored therein is not lost.
In order, then, for a PSRAM to behave like an SRAM, a refresh request can be attended to only when there is a restriction with regard to the read/write accesses initiated by the user or by the system environment. In normal operation, a refresh can be executed only when the memory circuit is deselected. A memory circuit is usually deselected if no read and write accesses to the memory circuit are performed. The memory circuit is usually selected by a memory selection signal.
If the memory circuit is kept active, i.e. selected, for a relatively long time, the following problem arises: after the refresh period has elapsed, a refresh request is output to the controller of the PSRAM. This cannot be processed, however, because the memory circuit is still active, i.e. an access is underway, or an access that is not permitted to be interrupted by a refresh access can be started at any time. After a further refresh period has elapsed, a further refresh request is made, which likewise cannot be processed as long as the memory circuit is selected. Therefore, the refresh requests can accumulate. Loss of information is imminent in the meantime since some or all of the memory cells can lose their information.
If the memory circuit is then deselected, it is possibly the case that not all of the refresh requests can be processed before a renewed read/write access is started. The consequence once again is that the refresh operations are not executed with the required refresh period, and data are thus lost.
PSRAMs are thus compatible with SRAMs under only specific restrictions. In other words, a disadvantage arises for PSRAMs because they cannot be used in all systems without additional technical outlay.
This problem has been avoided hitherto by defining specific additional restrictions (timing parameters) in the specifications for PSRAMs. If these restrictions are complied with, the DRAM memory situated in the PSRAM is guaranteed to be refreshed at regular intervals, so that no information is lost. Such restrictions may be, by way of example, the maximum time in which the memory circuit is selected, the time within which an address change with a new row address must have taken place, and the minimum time for an active write signal.